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Question

CONCLUSION
We designed a 16 bit high performance signed multiplier.
In this multiplier, modified radix 4 booth encoding algorithm
is used to reduce the number of partial products by half. The
booth encoder and booth selector circuits are designed using
MCML gate structure. By using MCML, only two gates are
used in Booth selector compared to four gates in equivalent
CMOS circuit. We used Wallace-tree structure for speed and
power improvement. In this tree, only full adders and half
adders are used. Different type of adders are used for different
sections of final adder. This hybrid architecture enables power
reduction with no performance penalty.

Answer 1

结论
我们设计了一个16位高性能带符号乘法器。在这个乘法器中，采用了修正过的4基数展位编码算法来将部分乘积减少到一半。展位编码和展位选择循环是基于MCML门结构设计的，我们使用了Wallace树结构来提高速度和功耗的性能。这种树结构仅仅运用半加器和全加器，在不同部分中采用了不同类型的加法器来构成整个全局加法器。这种混合式结构能够在不牺牲性能代价的前提下减少功耗。

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