用VHDL语言编写1-9计数器，要求没有按键按下之前，显示0而不是9，同时按键消抖！谢谢！

Question

如题所述

Answer 1

按键未按前是低电平0（若是高电平需把底层文件1中的clr<='0'改为clr<='1'）
底层文件1（1-9计数器）
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity cnt is
port(clk:in std_logic;
clr:in std_logic;
q:out std_logic_vector(3 downto 0));
end entity cnt;

architecture behav of cnt is
signal count:std_logic_vector(3 downto 0);
begin
process(clk)
begin
if(clr<='0') then count<="0000";
elsif(clk'event and clk='1') then
if(count<9) then
count<=count+1;
else count<="0001";
end if;
end if;
end process;
q<=count;
end behav;
底层文件2（按键消抖）
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity debounce_low is
port(clk:in std_logic;
key_in:in std_logic;
key_out: out std_logic);
end debounce_low;
architecture one of debounce_low is
signal dout1,dout2,dout3,buff:std_logic;
begin
process(clk)
begin
IF (clk'event and clk='1') THEN
dout1<=key_in;
dout2<=dout1;
dout3<=dout2;
buff<=not(dout1 or dout2 or dout3) and buff;
end if;
end process;
key_out<=dout1 or dout2 or dout3;
end one;
顶层文件
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity cnt_9 is
port(clkk:in std_logic;
key:in std_logic;
cq:out std_logic_vector(3 downto 0)
);
end entity cnt_9;
architecture behav of cnt_9 is
component qudou is
port(clk:in std_logic;
key_in:in std_logic;
key_out: out std_logic);
end component;
component cnt is
port(clk:in std_logic;
clr:in std_logic;
q:out std_logic_vector(3 downto 0));
end component;

signal a:std_logic;
begin
u1:qudou port map(clk=>clkk,key_in=>key,key_out=>a);
u2:cnt port map(clk=>clkk,clr=>a,q=>cq);
end behav;本回答被提问者采纳